1. Field of the Invention
The present invention relates to semiconductor design. In particular, the present invention relates to adding metal layers to a microprocessor to increase operating frequency and lower power consumption.
2. Background of the Related Art
Related art microprocessor designs have an interconnect stack in which signal wires in alternate metal layers are orthogonal to each other. A perspective block diagram is shown in FIG. 1, which illustrates the related art design. In interconnect stack is illustrated with layers 110, 120, 130 and 140. Metal layers 120 and 130 are illustrated with signal wires arranged in an orthogonal pattern as known in the related art, while metal layers 110 and 140 have been approximated by a plane.
FIG. 2 illustrates an axial view of a related art metal layer interconnect stack. Ground planes 202 and 204, in this example, are above and below layer 200, respectively. Layer 200 includes a plurality of signal wires including power supplies 210 at right and left ends, ground/return 212 and signal wire sets 220 and 230. Each signal wire set includes a plurality of signal wires 221–226 and 231–234, respectively. The first set 220 of six signal wires 221–226 is at a minimum pitch. The second set 230 of four signal wires 231–234 is at a 20% larger pitch. Those skilled in the art will appreciate that the illustrated arrangement is solely for purposes of illustration.
The related art topology creates problems in regard to the parasitic capacitance (i.e., the wire capacitance) on the signal wires. The wire capacitance decreases the potential operating frequency and increases the power consumed due to the capacitive load. Since the operating frequency of semiconductor devices is constantly increasing, reducing the wire capacitance of the signal wires allows for increased frequency and reduced power consumption, particularly on high frequency signal wires that are limited in the related art architecture.